reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for deviceconfiguration as well as readback of status registers. The CD97D39 is manufactured on a 0.18μm CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics.
- Resolution(Bits):14
- Channel:1
- Sample rate(Msps):2500
- Interface Type:LVDS
- SFDR(dB): 70
-
Third-order intermodulation(dB):87
-
ACLR(dB):82
- Noise spectral density(dB/hz):-
- Power consumption:950 mW
- Supply Voltage:1.8 V / 3.3 V
-
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix mode
-
Industry leading single/multicarrier IF or RF synthesis
fOUT = 350 MHz, ACLR =80 dBc
fOUT = 950 MHz, ACLR = 78 dBc
fOUT = 2100 MHz, ACLR = 69 dBc
-
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
-
Multichip synchronization capability
-
Programmable output current: 8.7 mA to 31.7 mA
-
Low power: 1.16 W at 2.5 GSPS
-
Broadband communications systems
-
Military broadband electronic system
-
Instruments and automatic test equipment
-
Radar and aviation equipment
-
CMTS system equipment
Datasheet
Datasheet
