CD1001 is a cost-effective fast Ethernet controller chip that integrates 10/100M PHY and MAC layers. It has a built-in 16K byte SRAM and provides a universal processor access interface to the outside world. This chip has excellent characteristics of low power consumption and high performance, supports 3.3V IO level, and can accept 5V input IO voltage.
CD1001 supports 8-bit and 16 bit data interfaces for accessing internal SRAM. The built-in PHY can support UTP3,4,5 10Base-T and UTP5 100Base-TX. Fully compliant with IEEE 802.3u specifications. Support automatic negotiation function.
- Supply:3.3V & 5V
- Interface:Support media independent interfaces
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PHY:10M/100M
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TCP/IP Protocol stack:IEEE802.3x
- Package:TQFP-48
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48-pin TQFP
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Supports processor interface: byte/word of I/O command to internal memory data operation
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Integrated 10/100M transceiver with HP Auto-MDIX
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Supports back pressure mode for half-duplex mode flow control
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IEEE802.3x flow control for full-duplex mode
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Supports wakeup frame, link status change and magic packet events for remote wake up
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Support 100M Fiber interface.
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Integrated 16K Byte SRAM
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Build in 3.3V to 2.5V regulator
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Supports early Transmit
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Supports automatically load vendor ID and product ID from EEPROM
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Supports IP/TCP/UDP checksum generation and checking
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Optional EEPROM configuration
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Very low power consumption mode: –Power reduced mode (cable detection) –Power down mode--Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. Compatible with 3.3V and 5.0V tolerant I/O
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Home network equipment: set top box, personal video recorder, digital media adapter
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Serial to Ethernet: access control, LED display, wireless AP relay, etc. Parallel to Ethernet: POS / micro printer, copier
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USB to Ethernet: storage device, network printer
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GPIO to Ethernet: home network sensor
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Security system: digital video recorder, network camera, information kiosk Factory and building automation control system
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Medical monitoring equipment
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Embedded Server
Datasheet
