CD16AD125 is a dual-channel, 16-bit, 125 / 105 / 80 MSPS Analog-to-Digital Converter (ADC), designed to meet the requirements of high-performance, low-cost, and compact multi-functional communication applications. The dual-channel ADC core adopts a multistage differential pipeline architecture, with each ADC integrating a high-bandwidth differential sample-and-hold circuit, supporting a variety of user-selectable input ranges.
The chip internally integrates reference voltage sources, simplifying external design. A duty cycle stabilizer is available to compensate for variations in the ADC clock duty cycle, maintaining excellent converter performance. The ADC output data can be directly sent to two external 16-bit output ports, supporting both 1.8V CMOS and LVDS modes. Flexible power-down options significantly reduce power consumption. A three-wire SPI-compatible serial interface can configure various functions of the product.
CD16AD125 is available in a 64-pin QFN package, with a rated temperature range of -40°C to +85°C for industrial applications.
- Resolution: 16 bit
- Channels: 2 Channel
- Interface: Parallel
- Sample Rate(Msps): 125 / 105 / 80
- Input Type: Differential
- Architecture: Pipeline
- Analog Supply Voltage: 1.8 V
- Digital Supply Voltage: 1.8 V
- SNR – Signal to Noise Ratio: 78 dB
- Operating Temperature -40 ℃ - 85 ℃
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Signal to Noise Ratio(SNR)：78 dBFS
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Spurious-Free Dynamic Range(SFDR)：88 dBc
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Low power consumption：800 mW (125 MSPS)
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1.8 V analog power supply
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1.8 V CMOS or LVDS output power supply
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1 to 8 integer input clock divider
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IF sampling frequency up to 300 MHz
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Small-signal input noise: −153.6 dBm/Hz (200 Ω input impedance, 70 MHz, 125 MSPS)
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Optional on-chip dither
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Radar System
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Diversity Radio System
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Multimode Digital Receiver (3G)
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GSM/EDGE/W-CDMA/LTE/CDMA2000 WiMAX/TD-SCDMA
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I/O Demodulation Systems
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Intelligent antenna system
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Universal Software Defined Radio
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Broadband Data Applications
- Ultrasound equipment
Datasheet
Datasheet
Datasheet
