The CD96AD56-125 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample and hold circuit designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. An external reference or driver components are not required for many applications. Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility andminimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
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Resolution(Bits): 16
- Channel:4
- Interface Type:JESD204B
- Sample rate(Msps): 125
- Input Type: Differential
- Structure Type: Pipeline
- Analog Supply Voltage: 1.8 V
- Digital Supply Voltage: 1.8 V
- SNR: 79 dB
- Operationing temperature range -40 ℃~+85 ℃
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SNR：79dBFS (9.7MHz, VREF=1.4V)
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SNR：77dBFs (9.7MHz, VREF=1.0V)
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SFDR：85dBc to Nyqulst(VREF=1.4V)
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SFDR：91dBc to Nyqulst(VREF=1.0V)
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JESD204B Subclass 1 coded serial digital outputs
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Flexible analog input range: 2.0 V p-p to 2.8 V p-p
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1.8 V supply operation
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Low power: 195 mW per channel at 125 MSPS (two lanes)
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DNL = ±0.6 LSB (VREF = 1.4 V)
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INL = ±5.0 LSB (VREF = 1.4 V)
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650 MHz analog input bandwidth, full power
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Serial port control
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Full chip and individual channel power-down modes
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Built-in and custom digital test pattern generation
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Multichip sync and clock divider
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Standby mode
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High speed imaging
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Quadrature radio receivers
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Diversity radio receivers
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Portable test equipment
Datasheet
