CD94AD34 is a 12 bit, single-chip sampling analog-to-digital converter (ADC) optimized for high performance, low power consumption, and ease of use. Its conversion rate can reach 500 MSPS, and it has good dynamic performance in broadband applications. All required functions are integrated on the chip, including sampling and holding amplifiers (SHA) and on-chip reference voltage sources, to provide a complete signal conversion solution. The VREF pin can be used to change the internal reference voltage or receive a reference voltage from the outside (the external reference mode needs to be turned on through the SPI port).
This ADC requires a 1.8V analog power supply and a differential clock to maintain excellent overall ADC performance. The digital output is compatible with LVDS (ANSI-644) and the data format is binary complement, Gray code, or offset binary. There is a data output clock to ensure that the corresponding data output has the correct timing.
This product is manufactured using SiGe BiCMOS technology, with 56 lead plastic packaging (QFN56), which can effectively replace ADI's AD9434BCPZ in the United States.
- Resolution (Bits): 12
- Number of channels:1
- Sampling rate (Msps):500, 370
- Interface type:Serial port control
- SNR - signal-to-noise ratio:63 dBFS
- Power consumption:900 mW
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Architecture type:Pipeline
- Power supply range:1.8 V
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Signal to Noise Ratio (SNR): 65 dBFS (fIN up to 250MHz, 500 MSPS)
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ENOB: 10.5 bits (fIN up to 250 MHz, 500 MSPS, − 1.0 dBFS)
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SFDR: -78 dBc (fIN up to 250 MHz, 500 MSPS, − 1.0 dBFS)
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Integrated input buffer
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Excellent linearity
Differential nonlinearity (DNL): ± 0.5 LSB (typical value)
Integral nonlinearity (INL): ± 0.6 LSB (typical value)
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Provide LVDS output at 500 MSPS (ANSI-644 level)
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1 GHz full power analog bandwidth on-chip reference voltage source without external decoupling
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low power consumption
690 mW (500 MSPS) - LVDS SDR mode
660 mW (500 MSPS) - LVDS DDR mode
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Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p (nominal value)
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1.18 V p-p to 1.6 V p-p, 1.5 V p-p (nominal value)
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Optional output data formats (offset binary, binary complement, Gray code)
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Clock duty cycle stabilizer
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Integrated data clock output with programmable clock and data alignment function
- Wireless and wired broadband communication
- Cable reversal path
- Communication testing equipment
- Radar and satellite subsystems
- Power amplifier linearization
Datasheet
Datasheet
